Sage Any hacks to underclock Kobo Sage?

[TrueHit]

I believe having the 4 cores is what drains the battery more than the average eReader.
Is there a way to undervolt or even disable 2 of the 4 cores?

[Quoth]

It's not got a huge battery* and a frontlight on will use much more power than a 6″ ereader.
Also avoid WiFi and BT.
If the frontlight, WiFi and BT are off it sleeps almost entirely when you are reading and wakes when you turn the page, so disabling cores or messing with CPU performance won't make much difference.

It's also likely it only uses all the cores when using the Advanced Notebook and you are writing.

The battery (cell really) life is much as expected for 8″ (more power to turn page than 6″) with the size of battery and frontlight, WiFi and BT are off. That's how I use it and find no issue with run time at all.

You probably can't run the CPU at a lower voltage. However power is related to clock speed squared, so half clock speed in theory is 1/4 power, but I'd not recommend trying it.
Being able to change the cores in use is unlikely.

[* The battery isn't as big as it ought to be. Possibly they thought that people would buy the power cover, which oddly doesn't work well. A power bank works better. Some of the Oasis (1st is 6″, next 2 are 7″) have the same flaw and also the Oasis was intended to have a power cover]


I reported your other post as a duplicate.

[NiLuJe]

Nickel already offlines the cores as necessary (it will hardly ever online the 4 cores, even note-taking is usually only pegged at 3). And the system already handles frequency & voltage scaling on its own. The power efficiency of this SoC (or at least this implementation of it) is just hilariously bad, Nickel is already doing the best it can with it.

[Quoth]

Originally Posted by NiLuJe

Nickel already offlines the cores as necessary (it will hardly ever online the 4 cores, even note-taking is usually only pegged at 3). And the system already handles frequency & voltage scaling on its own. The power efficiency of this SoC (or at least this implementation of it) is just hilariously bad, Nickel is already doing the best it can with it.

That's what I guessed. However the battery cell ought to be bigger? The PCB and cable for the external power cover wastes space and the load of big magnets for the power cover waste space and add to weight. A worse design decision than the SoC.