Quote:
Originally Posted by ixtab
Could you give me a hint as to which file I should start looking at?
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Starting point for your task is
board/imx50_yoshi/flash_header.S. Search for comment string:
Code:
/*=============================================================================
*init script for codex LPDDR1-200MHz CPU board
*===========================================================================*/
It's where Yifan Lu copied his code from. At first it's necessary to apply workaround for PLL meta-stability issue. It's an official bug (with no fix scheduled) and it's related to DDR. It's described in i.MX50 chip errata (search in Google for
IMX50CE.pdf and then take a look at section
ENGcm12051 at this document).
Then, there is
Enable all clocks code, but, I believe, all clocks are already enabled in boot process (BTW, PLL1 is set up at 800 MHz automatically too). It's according to chapters 6.4.3, 6.4.4 and tables 6-5 and 6-6 from Reference Manual.
But I can be deadly wrong.
And then there is a jump to DDR init code. Code is located at
board/imx50_yoshi/ram_init.S. Search for
label lpddr2_init: label
mddr_init: at that source file (
why mddr_init?).
(Well, I was wrong. DDR intialization is expressed through code, not DCD commands. But anyway, process of writing to registers is perfectly mapped to DCD capabilities. If you're interested, look at chapter 6.6.2 of Reference Manual).
Also, just to be clear, I was speaking about U-Boot from 5.1.2 sources.