Quote:
Originally Posted by Quoth
True, but simpler to have both at the component level. Similarly while And and Or are basic operations real devices use Nand and Nor (Valves, RTL, TTL, CMOS etc).
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In practice, for hand-designed gate level logic, one or the other is generally used, not both. The logic optimisation typically results in a sum-of-products expression (AND-OR, which de-morganises to NAND-NAND), or a product-of-sums (OR-AND, which de-morganises to NOR-NOR). In practice it's usually NAND-NAND that is chosen - at least in CMOS designs, which covers the vast majority of digital logic today (CMOS NAND gates have better symmetry of rise and fall times than NOR gates, when same-size MOSFETs are used). Most hand designs will involve a mixture of NAND gates and edge-triggered D-type flip-flops.
Of course, the vast majority of digital design these days isn't done by hand at gate level - it's usually done at RTL level in an HDL such as system verilog or VHDL and synthesised. Depending on the target, the synthesised output may be NAND gates and d-types, but it often isn't - e.g. if it's to FPGA the basic cell from which it's all built is usually a look-up-table for the combinatorial logic, a flip-flop, and a 2 input mux. Other target types like PLAs have their own structures. (Not to mention that in practice much of the logic is just done in software these days, as embedded microcontrollers are so easy to include in custom digital designs.)