Quote:
Originally Posted by knc1
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Edit-4:
Added tech. sheet on level translation chip.
Decided on setting up the layout to hold 2, 2 bit wide, level translators.
Which seems to be the most generally useful layout, even though we only need one (or maybe two) bits worth (I.E: a single chip) worth of translation.
This chip will handle any (common) logic level found in today's logic (except 1v2 and 1v5 cell phones) and translate it to any of the choosen adapter chip's i/o levels (1v8, 3v3 or 5v0).
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My preliminary guess at a standard I/O level translator part.