Due to the overwhelming non-response from PW2 owners, I will drop that from consideration for now at least.
For use in the KT2 - the MicroFTX board really needs to be built in a low profile version.
I.E: Currently has a surface mount micro-usb connector, needs to have a micro-usb connector that mounts with its centerline on the board centerline (like at least some kindles have).
For now, I will just fake it by physically hacking up a high profile version into a low profile version.
Lucky for us, Jim Paris has OpenSourced all of his design files:
http://jim.sh/ftx/#design-files
The PCB board layout requires (at least) Eagle V.6:
http://www.cadsoftusa.com/download-eagle/?language=en
But I think that the "Freeware" version should also work:
http://www.cadsoftusa.com/download-e...e/?language=en
EDIT:
Confirmed, the "Freeware" version (for Linux) easily handles the Jim Paris files (in the *.zip archive).
(The *.pdf files are **OUTPUTS** of the board layout program.)
- - - - - -
Next development step (skipping over the days of work between now and then):
The board breaks out 4 of the 'cb' pins -
This far I have only committed to using 2 of them (reset and on/off) -
They can be programmed as inputs (also) -
I will set the other two as inputs, and use them to monitor the levels on the two "USB boot" leads beginning with a hardware reset.
Expected:
That they will be the "boot mode" leads during reset -
The "boot mode" leads will be scanned by the hardware during reset -
After reset, they may (or may not) be re-programmed as other signals (the PW2 silk screen seems to indicate that one of them becomes one of the JTAG leads).
The boot mode leads are not multiplexed, but then these may not be the actual boot mode leads from the SoC.
But I suspect the hardware around them is setup so that the same type of single pole, momentary contact, switch was used to just hold the two leads connected during the reset scan, and to do no harm if held (or pushed) after the reset scan completes.
(They used (or are using) the same board for development as for production. We will learn if lab126 has shot themselves in the foot (again) with that decision.
)
Edit-2:
Added drawing of typical mid-mount, micro-usb connector for the low profile adapter board as attachment-5.
Edit-3:
Added tech. sheet on switch chip.
The MicroFTX "cb" outputs are open-drain with a 75k ohm pull-up.
So far, the chip's I/O cells are referenced to 1v8 (since that matches the serial port I/O levels).
But the boot-mode lines need to be connected together (I am assuming here) to emulate a mechanical switch.
Plus, they are running on the 3v3 supply rail(s).
Hence, the added-in, switch chip.
And since they come in four per package ...
There are enough for all four "CB" outputs, if required by another project.
Edit-4:
Added tech. sheet on level translation chip.
Decided on setting up the layout to hold 2, 2 bit wide, level translators.
Which seems to be the most generally useful layout, even though we only need one (or maybe two) bits worth (I.E: a single chip) worth of translation.
This chip will handle any (common) logic level found in today's logic (except 1v2 and 1v5 cell phones) and translate it to any of the choosen adapter chip's i/o levels (1v8, 3v3 or 5v0).