Quote:
Originally Posted by hawhill
A short addendum: In k3flasher, I do the "mDDR init limbo" - as a straight reimplementation of what ATK does. That said, I never looked into the SoC reference manual to actually look up _what_ they are doing there. It might be that the timing they use is specifically suited for Freescale's iMX development board, but needs to be just a tad bit different for a Kindle - so what we experience here is a RAM running a bit out of its specified timing (which might work or not). This is just poking with a stick in the dark, however.
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Worth taking a look at, once we have "clean code" in the RAM kernel.
Thanks for the suggestion, we should be able to get the DDR settings out of the U-Boot source or out of the DDR rom.